IA82527
Data Sheet
CAN Serial Communications Controller
December 20, 2012
Table 3. Pin/Signal Descriptions (Continued)
Pin
Signal
int_n
Name
PLCC PQFP
Description
int_n/ VCC/2
int_n/p2.6
24
11
18
5
interrupt. Output (open collector). Active Low. On the
IA82527, two pins can provide the interrupt (int_n)
output; however, depending on the setting of the MUX
bit in the CPU Interface Register (02H), only one of the
pins will serve as the source of int_n as follows:
• PLCC Package:
–
When the MUX bit of the CPU Interface Register
is 0, pin 24 functions as the int_n output and pin
11 functions as p2.6.
–
When the MUX bit of the CPU Interface Register
is 1, pin 11 functions as the int_n output and pin
24 functions as Vcc/2.
• PQFP Package:
–
When the MUX bit of the CPU Interface Register
is 0, pin 18 functions as the int_n output and pin
5 functions as p2.6.
–
When the MUX bit of the CPU Interface Register
is 1, pin 5 functions as the int_n output and pin
18 functions as Vcc/2.
miso
ready/miso
28
22
master in slave out. Output (open drain). Serial
Interface Mode. When the IA82527 is configured to
operate with a serial interface, miso is the serial data
output.
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