IA82527
Data Sheet
CAN Serial Communications Controller
December 20, 2012
Table 3. Pin/Signal Descriptions (Continued)
Pin
Signal
ale
Name
ale/as
PLCC PQFP
Description
5
43
address latch enable. Input. Active High. Mode 0 and
Mode 1. When the IA82527 is configured to operate in
either the 8-bit multiplexed Intel architecture mode
(Mode 0) or the 16-bit multiplexed Intel architecture
mode (Mode 1), this signal latches the address into the
device during the address phase of the bus cycle.
as
ale/as
5
43
address strobe. Input. Active High. Mode 2. When
the IA82527 is configured to operate in the 8-bit
multiplexed non-Intel architecture mode (Mode 2), this
signal latches the address into the device during the
address phase of the bus cycle.
If the IA82527 is configured to operate in Mode 3 (8-bit
non-multiplexed non-Intel architecture), this pin must
be tied high.
clkout
clkout
27
21
clock out. Output (push-pull). This output provides a
programmable clock frequency. The frequency is set
via the Clockout Register (1FH) and can range from
the frequency of the xtal (crystal) input to xtal/n, where
n can be an integer value from 2 through 15. This
output allows the IA82527 to clock other devices such
as the host CPU.
For 3.3V operation the crystal or external oscillator
must run at <=12 MHz to produce clock output.
cp
a1/ad1/cp
cs_n
3
8
41
2
clock phase. Input. Serial Interface Mode. When this
input is a logic 0, data is sampled on the rising edge of
sclk. When this input is a logic 1, data is sampled on
the falling edge of sclk.
cs_n
chip select. Input. Active Low (Modes 0–3);
Selectable Active Level (Serial Interface Mode). When
the IA82527 is configured to operate in one of the
parallel interface modes (Modes 0–3) or the Serial
Interface Mode, this input, during its active state,
selects the device allowing CPU access.
For Serial Interface Mode operation, the active state is
selectable (i.e., either high or low) via the IA8257 csas
pin.
csas
a2/ad2/csas
2
40
chip select active state. Input. Serial Interface Mode.
When this input is a logic 0, the cs_n input is
configured to function active low. When this input is a
logic 1, the cs_n input is configured to function active
high.
IA211080504-07
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