IA82527
Data Sheet
CAN Serial Communications Controller
December 20, 2012
Table 3. Pin/Signal Descriptions (Continued)
Pin
Signal
Name
PLCC PQFP
Description
d0
d1
ad8/d0/p1.0
ad9/d1/p1.1
ad10/d2/p1.2
ad11/d3/p1.3
ad12/d4/p1.4
ad13/d5/p1.5
ad14/d6/p1.6
ad15/d7/p1.7
38
37
36
35
34
33
32
31
9
32
31
30
29
28
27
26
25
3
data bits 7–0. Input/Output. Mode 3. When the
IA82527 is configured to operate in the 8-bit
non-multiplexed non-Intel architecture mode (Mode 3),
these lines provide the 8-bit data bus to the device.
d2
d3
d4
d5
d6
d7
dsack0_n
dsack0_n
data and size acknowledge 0. Output. Active Low
(open drain with active pull-up). Mode 3
(asynchronous operation). When the IA82527 is
configured to operate in the 8-bit non-multiplexed
non-Intel architecture mode (Mode 3), this signal
functions as follows: when the CPU reads from the
IA82527, dsack0_n active low indicates that the data
is valid; when the CPU writes to the IA82527,
dsack0_n active low indicates that the data has been
received.
Note: The active pull-up circuitry drives dsack0_n
high for 10ns to raise it to a 3.0V voltage level. After
that, an external pull up is required to pull dsack0_n
the remainder of the way to VSS.
e
rd_n/e
6
4
44
42
enable. Input. Active High. Mode 3 (synchronous).
When the IA82527 is configured to operate in the 8-bit
non-multiplexed non-Intel architecture mode (Mode 3),
this signal functions as follows: when the CPU reads
from or writes to the IA82527, e active high indicates
that the address is valid.
icp
a0/ad0/icp
idle clock polarity. Input. Serial Interface Mode.
When this input is a logic 0, the polarity for the idle
state of sclk is low. When this input is a logic 1, the
polarity for the idle state of sclk is high.
IA211080504-07
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