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IA80C152
Preliminary Data Sheet
UNIVERSAL COMMUNICATIONS CONTROLLER
The IA80C152 is a "plug-and-play" drop-in replacement for the original IC. innovASIC produces
replacement ICs using its MILESTM, or Managed IC Lifetime Extension System, cloning technology.
This technology produces replacement ICs far more complex than "emulation" while ensuring they
are compatible with the original IC. MILESTM captures the design of a clone so it can be produced
even as silicon technology advances. MILESTM also verifies the clone against the original IC so that
even the "undocumented features" are duplicated. This data sheet documents all necessary
engineering information about the IA80C152 including functional and I/O descriptions, electrical
characteristics, and applicable timing.
INTEL is a registered trademark of Intel Corporation
DESCRIPTION
The IA80C152 is a Universal Communications Controller (UCC) that is pin-for-pin compatible
with the Intelä 80C152. This version of the UCC is a ROMless version. The ROM version is
identified as the 83C152 and can be easily derived from the 80C152 using a customer furnished
ROM program. The IA80C152 can be programmed with the same software development tools and
can transmit and receive using the same communication protocols as the Intelä 80C152 making the
IA80C152 a drop-in replacement. Table 1 below cross-references IA80C152 versions with
protocol, package, and I/O Port capability. Pinout diagrams are provided in figures 1, 2, and 3.
Table 1 - IC Version Differences
CSMA/CD,
innovASIC
Part Number
IA80C152JA
IA80C152JB
IA80C152JC
IA80C152JD
SDLC/HDLC,
User-Defined
5 I/O 7 I/O
Ports Ports
48 Pin DIP
68 Lead LCC
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Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
Ö
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The only difference between The innovASIC 80C152 and the Intelä 80C152 is that all protocols
are available in all IC versions. Originally, the Intelä 80C152 JC and JD versions were limited to
SDLC/HDLC only. Also, innovASIC will support a ROM version (83152) in any of the JA, JB, JC,
or JD versions.
The IA80C152 is partitioned into three major functional units identified as the C8051, the Direct
Memory Access (DMA) Controller, and the Global Serial Channel (GSC). The C8051 is
implemented using a CAST, Inc. Intellectual Property (IP) core. This core is instruction set
compatible with the 80C51BH, and contains compatible peripherals including a UART interface
and timers. The special function registers (SFRs) and interrupts are modified from the original
8051BH to accommodate the additional DMA controller and GSC peripherals.
The DMA Controller is a 2 channel, 8-bit device that is 16-bit addressable. Either channel can
access any combination of reads and writes to external memory, internal memory, or the SFR's.
Various modes allow the DMA to access the UART, GSC, SFRs, and internal and external memory
as well as provide for external control. Since there is only 1 data/program memory bus, only one
DMA channel or the microcontroller can have control at any give time. Arbitration within the
device makes this control transparent to the programmer.
Copyright ã 2000
innovASIC
[_________The End of Obsolescenceä
INNOVASIC [ INNOVASIC, INC ]
