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IA80C152
Preliminary Data Sheet
UNIVERSAL COMMUNICATIONS CONTROLLER
FEATURES
·
·
Two-Channel DMA With Multiple
Transfer Modes
·
Form, Fit, and Function Compatible
with the Intel 80C152
GSC Provides Support for Multiple
Protocols
·
Packaging options available
-
-
48 Pin Plastic or Ceramic DIP
68 Pin Plastic or Ceramic LCC
-
-
-
CSMA/CD
SDLC/HDLC
User Definable
·
·
8051 Core with:
-
-
-
-
-
Direct Memory Access(DMA)
Global Serial Channel (GSC)
MCS - 51 Compatible UART
Two Timers/Counters
·
·
Separate Transmit & Receive FIFOs
Special Protocol Features
-
-
-
-
-
Up to 2.0625 Mbps Serial
Operation
CSMA and SDLC Frame Formats
with CRC Checking
Manchester, NRZ, & NRZI Data
Encoding
Collision Detection & Resolution
in CSMA Mode
Maskable Interrupts
Memory
-
-
-
256 Bytes Internal RAM
64K Bytes Program Memory
64K Bytes Data Memory
·
·
5 or 7 I/O Ports
Up to 16.5 MHz Clock Frequency
Selectable Full/Half Duplex
(GRXD) P1.0
(GTXD) P1.1
(DENn) P1.2
(TXCn) P1.3
(RXCn) P1.4
(HLDn) P1.5
(HLDAn) P1.6
P1.7
(1)
(48)
(47)
(46)
(45)
(44)
(43)
(42)
(41)
(40)
(39)
(38)
(37)
(36)
(35)
(34)
(33)
(32)
(31)
(30)
(29)
(28)
(27)
(26)
(25)
VDD
IA80152
(2)
P4.0
48 Pin DIP
JA/JC
(3)
P4.1
(4)
P4.2
(5)
P4.3
(6)
P4.4
(7)
P4.5
(8)
P4.6
RESETn
(9)
P4.7
(RXD) P3.0
(TXD) P3.1
(INT0n) P3.2
(INT1n) P3.3
(T0) P3.4
(10)
(11)
(12)
(13)
(14)
(15)
(16)
(17)
(18)
(19)
(20)
(21)
(22)
(23)
(24)
EA
ALE
PSENn
P2.7 (A15)
P2.6 (A14)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)
P0.7 (A / D7)
P0.6 (A / D6)
P0.5 (A / D5)
P0.4 (A / D4)
(T1) P3.5
(WRn) P3.6
(RDn) P3.7
(A / D0) P0.0
(A / D1) P0.1
(A / D2) P0.2
(A / D3) P0.3
XTAL2
XTAL1
Vss
Figure 1 - 48 Pin DIP Pinout
Copyright ã 2000
innovASIC
[_________The End of Obsolescenceä
INNOVASIC [ INNOVASIC, INC ]
