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IA80C152
Preliminary Data Sheet
UNIVERSAL COMMUNICATIONS CONTROLLER
Table 4 - SFR Summary
Register
Name
TFIFO
TH0
TH1
TL0
TL1
TMOD
TSTAT
Register
Address
085h
Functional
Block
GSC
Initial
Value
Item
52.
Description
Transmit FIFO
X
00h
00h
00h
00h
00h
53.
54.
55.
56.
57.
58.
08Ch
08Dh
08Ah
08Bh
089h
C8051
C8051
C8051
C8051
C8051
GSC
Timer (High) 0
Timer (High) 1
Timer (Low) 0
Timer (Low) 1
Timer Mode
0D8h
Transmit Status
XX000100b
Table 5 - Interrupt Summary
Priority
Symbol
Name
Enable
Symbol
Name
Interrupt
Priority
Interrupt
Name
Priority
Address
Enable
Address
Vector
Address
-
1
2
3
4
5
6
7
8
Enable All Interrupts
External Interrupt 0
GSC Receive Valid
Timer 0 Overflow
GSC Receive Error
DMA Channel 0 Done
External Interrupt 1
GSC Transmit Valid
DMA Channel 1 Done
Timer 1 Overflow
-
EA
EX0
-
0AFh
-
PX0
PGSRV
PT0
PGSRE
PDMA0
PX1
PGSTV
PDMA1
PT1
0B8h
0F8h
0B9h
0F9h
0FAh
0BAh
0FBh
0FCh
0BBh
0FDh
0BCh
0A8h
0C8h
0A9h
0C9h
0CAh
0AAh
0CBh
0CCh
0ABh
0CDh
0ACh
03h
2Bh
0Bh
33h
3Bh
13h
43h
53h
1Bh
4Bh
23h
EGSRV
ET0
EGSRE
EDMA0
EX1
EGSTV
EDMA1
ET1
EGSRE
ES
9
10
11
GSC Transmit Error
UART Transmit/Receive
PGSRE
PS
Power Conservation Modes
There are 2 power conservation modes identified as Idle Mode and Power Down Mode. The
IA80C152 pins will have values according to the Table 6 below.
Idle Mode is entered through software control of the PCON register. Idle halts processor
execution and the DMA. The GSC continue to operate to the extent that it can without the
processor or DMA servicing its requests. Idle mode is exited upon receipt of any enabled interrupt
or invoking a hardware reset.
Power Down Mode is entered through software control of the PCON register. Power Down
disables the oscillator causing all functions to stop. RAM data is maintained since power is not
removed from the device. The only way to exit power down mode is to invoke a hardware reset.
Copyright ã 2000
innovASIC
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INNOVASIC [ INNOVASIC, INC ]
