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IA8044-PDW40I-00 参数 Datasheet PDF下载

IA8044-PDW40I-00图片预览
型号: IA8044-PDW40I-00
PDF下载: 下载PDF文件 查看货源
内容描述: SDLC通信控制器 [SDLC COMMUNICATIONS CONTROLLER]
分类和应用: 通信控制器光电二极管时钟
文件页数/大小: 32 页 / 135 K
品牌: INNOVASIC [ INNOVASIC, INC ]
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IA8044/IA8344  
SDLC COMMUNICATIONS CONTROLLER  
Preliminary Data Sheet  
As of Production Version 00  
I/O Characteristics  
The table below describes the I/O characteristics for each signal on the IC. The signal names  
correspond to the signal names on the pinout diagrams provided. The table below provides the  
I/O description of the IA8044 and the IA8344.  
Name  
RST  
Type  
Description  
I
Reset. This pin when held high for two machine cycles while  
the oscillator is running will cause the chip to reset.  
Address Latch Enable. Used to latch the address on the falling  
edge for external memory accesses.  
Program Store Enable. When low acts as an output enable for  
external program memory.  
ALE  
O
O
PSEN  
EA  
I
External Access. When held low EA will cause the  
IA8044/IA8344 to fetch instructions from external memory.  
Port 0. 8 bit I/O port and low order multiplexed address/data  
byte for external accesses.  
Port 1. 8 bit I/O port. Two bits have alternate functions, P1.6  
(RTS) and P1.7 (CTS).  
Port 2. 8 bit I/O port. It also functions as the high order  
address byte during external accesses.  
Port 3. 8 bit I/O port. Port 3 bits also have alternate  
functions as described below.  
P0.7 – P0.0  
P1.7 – P1.0  
P2.7 – P2.0  
P3.7 – P3.0  
I/O  
I/O  
I/O  
I/O  
P3.0 – RXD. Receive data input for SIU or direction control  
for P3.1 dependent upon datalink configuration.  
P3.1 – TXD. Transmit data output for SIU or data  
input/output dependent upon datalink configuration. Also  
enables diagnostic mode when cleared.  
P3.2 – INT0. Interrupt 0 input or gate control input for  
counter 0.  
P3.3 – INT1. Interrupt 1 input or gate control input for  
counter 1.  
P3.4 – T0. Input to counter 0.  
P3.5 – SCLK/T1. SCLK input to SIU or input to counter 1.  
P3.6 – WR. External memory write signal.  
P3.7 – RD. External memory read signal.  
Crystal Input 1. Connect to VSS when external clock is used  
on XTAL2. May be connected to a crystal (with XTAL2), or  
may be driven directly with a clock source (XTAL2 not  
connected).  
Crystal Input 2. May be connected to a crystal (with XTAL1),  
or may be driven directly with an inverted clock source  
(XTAL1 tied to ground).  
XTAL1  
XTAL2  
I
O
VSS  
VCC  
P
P
Ground.  
+5V power.  
Copyright  
2001  
ENG210010112-00  
www.innovasic.com  
innovASIC  
Customer Support:  
1-888-824-4184  
The End of Obsolescence  
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