IA8044/IA8344
SDLC COMMUNICATIONS CONTROLLER
Preliminary Data Sheet
As of Production Version 00
Functional Block Diagram
I/O for Memory, SIU, DMA, Interrupts, Timers
Port 0
ADDR/DATA/IO
Port 2
ADDR/DATA/IO
Port 1
SPCL FUNC/IO
Port 3
SPCL FUNC/IO
Memory
Control
Control
XTAL
Reset
Clock Gen.
& Timing
192x8Dual Port
RAM
C8051
CPU
Address/Data
Interrupts
SIU
Timers
Copyright
2001
ENG210010112-00
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