IA8044/IA8344
Data Sheet
SDLC Communications Controller
March 30, 2010
TRLAZ
RDn Low to Address Float
–
83
9
83
–
9
ns
ns
TWHLH RDn or WRn High to ALE High
TCLCL
TCLCL
Table 50. Serial Interface Characteristics
Symbol
TDCY
TDCL
TDCH
tTD
Parameter
Data Clock
Min Max Unit
420
184
184
–
–
–
–
125
–
ns
ns
ns
ns
ns
ns
Data Clock Low
Data Clock High
Transmit Data Delay
Data Setup Time
Data Hold Time
tDSS
tDHS
26
58
–
Table 51. External Clock Drive Characteristics
Symbol
Parameter
Min Max Unit
ns
TCLCL Oscillator Period 52
–
5.1
Memory Access Waveforms
The IA8044/IA8344 program memory read cycle, data memory read cycle, and data memory
write cycle are presented in Figures 13 through 15, respectively.
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