IA8044/IA8344
Data Sheet
SDLC Communications Controller
March 30, 2010
5.
AC Specifications
AC characteristics, external data memory characteristics, serial interface characteristics, and
external clock drive characteristics are provided in Tables 48 through 51, respectively.
TA = −40 C to +85 C, VDD = 5V 10%, VSS = 0V, Load Capacitance = 87pF
Table 48. External Program Memory Characteristics
Variable Clock
12 MHz Osc 1/TCLCL = 3.5 MHz to 12 MHz
Symbol
TLHLL ALE Pulse Width
TAVLL Address Valid to ALE Low
TLLAX Address Hold After ALE Low
TLLIV
Parameter
Min
171
75
74
–
83
254
–
0
–
91
–
-9
Max
–
–
–
298
–
–
215
–
76
–
373
–
Min
2TCLCL+4
TCLCL-8
TCLCL-9
Max
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ALE Low to Valid Instr. In.
ALE Low to PSENn Low
–
4TCLCL-35
TLLPL
TCLCL
3TCLCL+4
–
–
TPLPH PSENn Pulse Width
TPLIV
TPXIX
TPXIZ
PSENn Low to Valid Instr. In
Input Instr. Hold After PSENn
Input Instr. Float After PSENn
–
0
3TCLCL-35
–
–
TCLCL+8
–
TCLCL-7
TPXAV PSENn to Address Valid
TAVIV Address to Valid Instr. In
TAZPL Address Float to PSENn
TCY Machine cycle
–
5TCLCL-43
-9
–
–
996
–
12TCLCL
Table 49. External Data Memory Characteristics
Variable Clock
12 MHz Osc 1/TCLCL = 3.5 MHz to 12 MHz
Symbol
TRLRH
TWLWH WRn Pulse Width
TLLAX
TRLDV
Parameter
RDn Pulse Width
Min
487
487
74
–
0
–
–
–
250
325
76
563
86
Max
–
–
–
383
–
165
633
708
250
–
Min
6TCLCL-13
6TCLCL-13
TCLCL-9
–
Max
–
–
–
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address Hold After ALE
RDn Low to Valid Data In
5TCLCL-35
TRHDX Data Hold After RDn
0
–
–
–
–
TRHDZ
TLLDV
TAVDV
TLLWL
Data Float After RDn
2TCLCL-2
8TCLCL-34
9TCLCL-42
3TCLCL
ALE Low to Valid Data In
Address to Valid Data In
ALE Low to RDn or WRn Low
3TCLCL
4TCLCL-8
TCLCL-7
7TCLCL-20
TCLCL+3
TAVWL Address to RDn or WRn Low
TQVWX Data Valid to WRn Transition
TQVWH Data Setup Before WRn High
TWHQX Data Held After WRn
–
–
–
–
–
–
–
®
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