IA8044/IA8344
Data Sheet
SDLC Communications Controller
March 30, 2010
Bit Processor
Int clk
T1 ovrflw
div by 2
DPLL
SCLK
RXD
Byte Processor
Bit timing
generator
zero insert/
Control State
Machine
Decision
Logic
start detect
delete
FCS
generator/
checker
NRZI encode/
decode
serial/parallel
shifter
TXD
Serial Information Bus
Internal Ram
SIU SFRs
Information Bus
Figure 11. Bit and Byte Processors
®
IA211010112-04
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