IA6805E2
29 August 2007
Microprocessor Unit
As of Production Version 00
The counter continues to count past zero, falling from $00 to $FF, and continues. The
processor may read the counter at any time without disturbing the count by reading the
timer data register (TDR). This allows a program to determine the length of time since a
timer interrupt has occurred. The timer interrupt request bit remains set until cleared by
software. The interrupt is lost if this happens before the timer interrupt is serviced.
The prescaler is a 7-bit divider used to extend the maximum length of the timer. TCR bits
0-2 are programmed to choose the appropriate prescaler output, which is used as the count
input. The prescaler is cleared by writing a “1” into TCR bit 3, which avoids truncation
errors. The processor cannot write to or read from the prescaler.
Timer Input Mode 1:
When TCR4 = 0 and TCR5 = 0, the input to the timer is from an internal clock and the
timer input is disabled. The internal clock mode can be used for periodic interrupt
generation as well as a reference for frequency and event measurement. The internal clock is
the instruction cycle clock and is coincident with Address Strobe (AS) except during the wait
instruction where it goes low. During the wait instruction the internal clock to the timer
continues to run at its normal rate.
Timer Input Mode 2:
When TCR4 = 1 and TCR5 = 0, the internal clock and timer input signal are ANDed to
form the timer input. This mode can be used to measure external pulse widths. The external
pulse turns on the internal clock for the duration of the pulse. The count accuracy in this
mode is ±1 clock. Accuracy improves with longer input pulse widths.
Timer Input Mode 3:
When TCR4 = 0 and TCR5 = 1, all inputs to the timer are disabled.
Timer Input Mode 4:
When TCR4 = 1 and TCR5 = 1, the internal clock input to the timer is disabled and the
timer input then comes from the external TIMER pin. The external clock can be used to
count external events as well as to provide an external frequency for generating periodic
interrupts.
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