IA63484
Data Sheet
Advanced CRT Controller
Figure 2: ACRTC Block Diagram
res_n
dreq_n
draw_adrs[19:0]
draw_data[15:0]
Register
Address
DMA
Control
Unit
20
16
dack_n
Drawing
Processor
Data
done_n
draw_en
write
draw_n
mrd
Interrupt
Control
irq_n
mad[15:0]
Unit
16
ma19_16_ra[3:0]
4
disp_adrs[19:0]
raster_adrs[4:0]
ra4
20
15
Display
Processor
CRT
Interface
16
d[15:0]
chr_int
ccud
chr
cs_n
lpstb
rs_n
lpstb
MPU
Interface
cud1_n, cud2_n
2
rw_n
gcud[1:0]
2
hsync
vsync
hsync_n
vsync_n
dtack_n
exsync
exsync_n
Timing
Processor
disp[1:0]
m_cyc
disp1_n, disp2_n
2
2
mcyc
as_n
as
clk2
clk_2
23
25
VSS
Vcc
ACRTC System Description:
Some CRT controllers provide a single bus interface to the frame buffer that must be shared with the host
MPU. However, refreshing large frame buffers, and accessing the frame buffer for drawing operations can
quickly saturate the shared bus.
The ACRTC uses separate host MPU and frame buffer interfaces. This allows the ACRTC full access to the
frame buffer for display refresh and drawing operations and minimizes the use of the MPU system bus by the
ACRTC. A related benefit is that a large frame buffer (2 MB for each ACRTC) can be used, even if the host
MPU has a smaller address space or segment size restriction.
The ACRTC can use an external Direct Memory Access Controller (DMAC) to increase system throughput
when many commands, parameters and data must be transferred to the ACRTC. Advanced DMAC features
such as the HD68450 “chaining” modes can be used to develop powerful graphics system architectures.
More cost-sensitive or less performance-sensitive applications might not require a DMAC. In these cases, the
interface to the ACRTC can be handled under MPU software control.
While both ACRTC bus interfaces (host MPU and frame buffer) are 16 bits wide, the ACRTC also offers an
8 bit MPU mode for easy connection to popular 8 bit busses.
Copyright ã 2001
innovASIC
ENG 21101041200
www.innovasic.com
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