IA63484
Data Sheet
Advanced CRT Controller
I/O SIGNAL DESCRIPTION:
The diagram below describes the I/O characteristics for each signal on the IC. The signal names
correspond to the signal names on the pinout diagrams provided.
I/O Characteristics:
Signal Name
res_n
I/O
I
Group
Description
ACRTC reset:
Data bus (three state): are the bidirectional data bus to the host mpu or dmac. D0 -D
are used in 8-bit data bus mode.
I/O
d[15,0]
rw_n
cs_n
I
I
Read/write strobe: controls the direction of host/ACRTC transformers.
Chip Select: enables transfers between the host and the ACRTC.
Register Select: selects the ACRTC register to be accessed. It is usually connected to
the least significant bit of the host address bus.
MPU
Interface
I
rs
Data transfer acknowledge (three state): output provides asynchronous bus cycle
timing. It is compatible with the HD68000 mpu dtack output.
Interrupt request (open drain): output generates interrupt service requests to the
host MPU.
DMA request: recieves DMA acknowledge timing from the host DMAC.
DMA acknoledge:
O
O
dtack_n
irq_n
dreq_n
dack
I
DMAC
I/O
Interface DMA done: terminates DMA transfer. It is compatible with the HD68450 DMAC
DONE signal.
I
I/O
O
done_n
clk_2
ARTC clock: is the baasic operating clock, twice the frequency of the dot clock.
Multiplexed frame buffer address/data bus: are the multiplexed frame buffer
address/data bus.
Address strobe: output demultiplexes the address/data bus.
Higer-order address bits/character screen rastar address:MA16/R0- MA19/RA3 are
the upper bits of the graphics screen ddress multiplexed with th lower bits of the
character screen raster address.
mad[15,0]
as_n
O
MA16/R0-*
MA19/RA3
O
Higer-order character screen rastar address bit: is the high bit of the character screen
raster address (up to 32 rasters.)
O
O
RA4
chr
Graphic or character screen access: output indicates whether a graphic or character
screen is being accessed.
Frame buffer memory acess timing signal: is the frame buffer access timing output,
CRT
O
O
O
mcyc
mrd
1/2 the frequency of clk_2.
Interface
Frame buffer memory read: output controls the frame buffer data bus direction.
Draw/refresh signal: output differentiates between drawing and CRT displayrefresh
cycles.
draw_n
Display enable: programmable display enable outputs can enable, disable, and blanck
logical screens.
O
disp1, disp2
Coursor Display: outputs provides cursor timing programmed by ACRTC parameters
such as cursor definition, cursor mode, cursor address, etc.
CRT vertical sync pulse: outputs the crt vertical synchronization pulse.
CRT horizontal sync pulse: outputs the crt horizontal synchronization pulse.
External sync:allows synchronization between multiple ACRTSs and other videro
signal generators.
cud1, cud2
vsync_n
hsync_n
O
I/O
I
exsync_n
lpstb
Lightpen strobe: is the lightpen input
Copyright ã 2001
innovASIC
ENG 21101041200
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