IA63484
Data Sheet
Advanced CRT Controller
Figure 5: Display Screen Specification
HC*
HWS*
HWW*
HDW*
HSW
HDS*
hsync_n
Display Screen Period
(Upper)
(Base)
(Window)
(Base)
(Lower)
Timing Processor:
The Timing Processor generates the CRT synchronization signals and signals used internally
by the ACRTC. The details for this block are contained in the module specification for the
Display Processor.
CRT Interface:
The CRT Interface manages the communication between the frame buffer, the light pen and the
CRT. The frame buffer interface manages the frame buffer bus and selects display drawing or
refreshes address outputs. The light pen interface uses a 20-bit address register and a strobe input pin
(lpstb).
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