IA21140AF
Preliminary Data Sheet
PCI FAST ETHERNET LAN CONTROLLER
PCI Other Signals:
Timing Diagram
Vtest*
clk
Tval (max)
Tval (min)
output
input
Ton
Toff
Th
Tsu
Note: Vtest is 1.5 V in a 5.0 V signaling environment and is
0.4 * vdd_clamp in a 3.3 V signaling environment.
Timing Characteristics
Symbol
Tval
Ton
Parameter
Min
Max
Unit
ns
clk-to-signal valid delay
2
2
-
11
-
Float-to-active delay from clk
Active-to-float delay from clk
Input signal valid setup time before clk
Input signal hold time from clk
ns
Toff
28
-
ns
Tsu
7
0
ns
Th
-
ns
Copyright 2001
innovASIC
ENG210010110-00
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