IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Table 86. Write Cycle Timing
a
a
No.
Name
Description
Min
Max
General Timing Responses
3
tCHSV
tCLSH
tCLAV
tCLAX
tCLDV
tCHDX
tCHLH
tLHLL
Status Active Delay
Status Inactive Delay
ad Address Valid Delay
Address Hold
0
10
10
10
10
10
–
4
0
5
0
6
0
7
Data Valid Delay
Status Hold Time
ale Active Delay
ale Width
0
8
0
9
0
10
–
10
11
12
13
14
16
17
18
19
20
22
23
15
tCHLL
tAVLL
ale Inactive Delay
0
10
–
ad Address Valid to ale Low
ad Address Hold from ale Inactive
ad Address Valid to Clock High
mcs_n/pcs_n Inactive Delay
mcs_n/pcs_n Hold from Command Inactive
mcs_n/pcs_n Inactive Delay
den_n Inactive to dt/r_n Low
Control Active Delay 1
tCLCH
tLLAX
tCHCL
–
tAVCH
tCLCSV
tCXCSX
tCHCSX
tDXDL
tCVCTV
tCHCTV
tLHAV
0
–
0
10
–
tCLCH
0
0
0
0
5
10
–
10
10
–
Control Active Delay 2
ale High to Address Valid
Write Cycle Timing Responses
30
31
32
33
34
35
65
67
68
87
tCLDOX
tCVCTX
tWLWH
tWHLH
tWHDX
Data Hold Time
0
–
10
–
Control Inactive Delay
wr_n Pulse Width
0
35
wr_n Inactive to ale High
Data Hold after wr_n
tCLCH-2
–
tCLCL
–
tWHDEX wr_n Inactive to den_n Inactive
12
–
tAVWL
tCHCSV
tCHAV
tAVBL
a Address Valid to wr_n Low
tCLCL + tCHCL-1.25
–
clkouta High to lcs_n/usc_n Valid
clkouta High to a Address Valid
a Address Valid to whb_n/wlb_n Low
0
10
10
–
0
tCHCL -1.25
a
In nanoseconds.
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