IA186ER/IA188ER
Data Sheet
16-Bit/8-Bit Microcontrollers with RAM
February 25, 2013
Table 85. Read Cycle Timing
a
a
No.
Name
Description
Min
Max
General Timing Requirements
1
2
tDVCL
tCLDX
Data in Setup
Data in Hold
6.6
2
–
–
General Timing Responses
3
4
5
6
8
9
tCHSV
tCLSH
tCLAV
tCLAX
tCHDX
tCHLH
Status Active Delay
0
10
10
10
10
–
Status Inactive Delay
ad Address Valid Delay
Address Hold
0
0
0
Status Hold Time
0
ale Active Delay
0
10
–
10 tLHLL
11 tCHLL
12 tAVLL
13 tLLAX
14 tAVCH
15 tCLAZ
ale Width
tCLCL-5
ale Inactive Delay
0
10
–
ad Address Valid to ale Low
ad Address Hold from ale Inactive
ad Address Valid to Clock High
ad Address Float Delay
tCLCH
tCHCL
–
0
–
0
15
10
–
16 tCLCSV mcs_n/pcs_n Inactive Delay
0
17 tCXCSX mcs_n/pcs_n Hold from Command Inactive
18 tCHCSX mcs_n/pcs_n Inactive Delay
tCLCH
0
0
0
0
0
5
10
–
19 tDXDL
den_n Inactive to dt/r_n Low
20 tCVCTV Control Active Delay 1
21 tCVDEX den_n Inactive Delay
22 tCHCTV Control Active Delay 2
10
14
10
–
23 tLHAV
ale High to Address Valid
Read Cycle Timing Responses
24 tAZRL
25 tCLRL
26 tRLRH
27 tCLRH
28 tRHLH
29 tRHAV
66 tAVRL
ad Address Float to rd_n Active
0
–
10
–
rd_n Active Delay
0
rd_n Pulse Width
tCLCL
rd_n Inactive Delay
0
10
–
rd_n Inactive to ale High
rd_n Inactive to ad Address Active
a Address Valid to rd_n Low
tCLCH
tCLCL-5
–
30
0
–
67 tCHCSV clkouta High to lcs_n/usc_n Valid
10
10
68 tCHAV
clkouta High to a Address Valid
0
a
In nanoseconds.
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