IA186XL/IA188XL
16-Bit Microcontrollers
Data Sheet
July 6, 2011
Workaround: When using external interrupts in cascade mode, do not program other interrupts
to have a high priority (except DMAs). When using both IRQ0 and IRQ1 in Cascade Mode they
must be programmed to have the same priority level.
Errata No. 4
Problem:
Memory->Memory moves interrupted by two DMA cycles can corrupt data.
Description:
This problem occurs if Memory->Memory operation is interrupted by
2 DMA cycles with the following sequence:
1. The instruction reads data from memory.
2. The first DMA cycle occurs.
3. The second DMA request occurs between 1 and 4 clocks after the falling edge of ALE for
the deposit phase of the first DMA.
4. An instruction fetch occurs (this will be the data that shows up later).
5. The second DMA cycle occurs.
6. The write phase of the instruction happens with bad data (from step 4).
If the second DMA request occurs earlier than 1 clock after ALE for the first DMA's deposit
phase, step 4 will be preempted by the second DMA, and operation is correct.
If the second DMA request occurs later than 4 clocks after ALE for the first DMA's deposit
phase, the write phase will follow step 4 immediately, and operation is correct.
Of the total 163 instructions, the following 8 are impacted by this issue, with both the 8 & 16 bit
versions of the first 7 on the list being affected.
1. MOVS
2. PUSH mem
3. POP mem
4. INS
5. IN
6. OUTS
7. OUT
8. ENTER
Workaround: If the conditions described above occur, there is no workaround. However, this
DMA issue will be corrected in Revision 1 of the device.
®
IA211080711-09
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