IA186XL/IA188XL
16-Bit Microcontrollers
Data Sheet
July 6, 2011
8.
Errata
The following errata are associated with the IA186XL/IA188XL. A workaround to the identified
problem has been provided where possible.
8.1
Summary
Table 24 presents a summary of errata.
Table 24. Summary of Errata
Errata
No.
Problem
Ver. 0
Ver. 1
Ver. 2
Pin LOCK_n does not have an internal pullup and
will float during reset and bus hold.
Exists
Exists
Exists
1
When the timer compare register for any of the
timers is set to x0000, the max count is xFFFF
instead of x10000 as in the OEM part.
Exists
Exists
Fixed
Fixed
Fixed
Fixed
2
3
When using external interrupts IRQ0 or IRQ1 in
Cascade Mode, the acknowledge signal on INTA0
or INTA1 may be lost or truncated.
Memory->Memory moves interrupted by two DMA
cycles can corrupt data.
Exists
Exists
Fixed
Fixed
Fixed
Fixed
4
5
Bit 15 of RELREG (offset 0xFE) behaves
differently than Intel device.
Enhanced mode makes bit 15 of RELREG (offset
0xFE) read-only.
Exists
Exists
Exists
Exists
Exists
Fixed
Fixed
Exists
Exists
Exists
Fixed
Fixed
Fixed
Fixed
Fixed
6
7
Sbus deasserts on the wrong edge of CLKOUT.
Timer2 count register must be written to enable
counting.
Non-maskable interrupt (NMI) can be pre-empted
by maskable interrupt.
8
9
DMA can hang.
10
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