IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
Bits [1–0]—R [1–0] → Wait-State Value. The value of these bits determines the number
of wait states inserted in an access. Up to three wait states can be inserted (R1–R0 = 00b
to 11b).
5.1.18 PACS (0a4h)
PeripherAl Chip Select Register. These Peripheral Chip Selects are asserted over 256-byte range
with the same timing as the ad address bus. There are six chip selects, pcs6_n–pcs5_n and
pcs3_n–pcs0_n that are used in either the user-locatable memory or I/O blocks. Excluding the
areas used by the ucs_n, lcs_n, and mcs_n chip selects, the memory block can be located
anywhere within the 1-Mbyte address space. These chip selects may also be configured to
access the 64-Kbyte I/O space.
Programming the Peripheral Chip Selects uses the Peripheral Chip Select (PACS) and the pcs_n
and mcs_n Auxiliary (MPCS) registers. The PACS register establishes the base address,
configures the ready mode, and determines the number of wait states for the pcs3_n–pcs0_n
outputs.
The MPCS register configures the pcs6_n–pcs5_n pins to be either chip selects or address pins
a1 and a2. When these pins are configured as chip selects, the MPCS register determines the
ready state and wait states for these output pins and whether they are active during memory or
I/O bus cycles. These pins are activated as chip selects by writing to the two registers (PACS
and MPCS). They are not active on reset. To configure and activate them as address pins, it is
necessary to write to both the PACS and MPCS registers. Pins pcs6_n–pcs5_n can be
configured for 0 to 3 wait states and pcs3_n–pcs0_n can be programmed for 0 to 15 wait states.
The value of the PACS register is undefined at reset (see Table 34).
Table 34. Peripheral Chip Select Register
15 14 13 12 11 10
9
8
7
6
1
5
1
4
1
3
2
1
0
BA19–BA11
R3 R2 R1–R0
Bits [15–7]—BA [19–11] → Base Address bits correspond to Bits [19–11] of the 20-bit
programmable base address of the peripheral chip select block and determine the base
address. Because I/O addresses are only 16 bits wide, if the pcs_n chip selects are
mapped to I/O space, these bits must be set to 0000b. The pcs address ranges are shown
below.
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