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AM188EM-20VIW 参数 Datasheet PDF下载

AM188EM-20VIW图片预览
型号: AM188EM-20VIW
PDF下载: 下载PDF文件 查看货源
内容描述: 8位/ 16位微控制器 [8-Bit/16-Bit Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 146 页 / 1574 K
品牌: INNOVASIC [ INNOVASIC, INC ]
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IA186EM/IA188EM  
Data Sheet  
8-Bit/16-Bit Microcontrollers  
February 25, 2011  
4.  
Device Architecture  
A functional block diagram of the IA186EM/IA188EM is shown in Figure 7. This  
microcontroller consists of the following functional blocks.  
Bus Interface and Control (BIC)  
Peripheral Control and Registers  
Chip Selects and Control (CSC)  
Programmable I/O  
Clock and Power Management  
DMA  
Interrupt Controller  
Timers  
Asynchronous Serial Ports  
Synchronous Serial Interface  
4.1  
Bus Interface and Control  
BIC manages all accesses to external memory and external peripherals. These peripherals may  
be mapped either in memory space or I/O space. The BIC supports both multiplexed and non-  
multiplexed bus operations. Multiplexed address and data are provided on the ad15ad0 bus,  
while a non-multiplexed address is provided on the a19a0 bus. The a bus provides address  
information for the entire bus cycle (t1t4), while the ad bus provides address information only  
during the first phase of the bus cycle (t1). For more details regarding bus cycles, see the AC  
waveforms at the end of this datasheet.  
The IA186EM microcontroller provides two signals that serve as byte write enables, write high  
byte (whb_n) and write low byte (wlb_n). The IA188EM microcontroller requires only a single  
write byte (wb_n) signal to support its 8-bit data bus. The whb_n is the logical OR of the bhe_n  
and wr_n. The wlb_n is the logical OR of ad0 and wr_n. The wlb_n is the logical OR of ad0  
and wr_n. The wb_n is low whenever a byte is written to the IA188EM data bus ad7ad0.  
The byte write enables are driven in conjunction with the non-multiplexed address bus a19a0 to  
support the timing requirements of common SRAMs.  
The BIC also provides support for PSRAM devices. PSRAM is supported in only the lower chip  
select (lcs_n) area. In order to support PSRAM, the CSC must be appropriately programmed  
(see Section 4.7, Chip Selects).  
®
IA211050831-19  
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