IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
Bits [R1–R0]—R [1–0] → Wait-State Value. The value of these bits determines the
number of wait states inserted into an access to the lcs_n memory area. This number
ranges from 0 to 3 (R1–R0 = 00b to 11b).
5.1.20 UMCS (0a0h)
The Upper Memory Chip Select Register configures the UMCS pin, used for the top of memory.
On reset, the first fetch takes place at memory location FFFF0h and thus this area of memory is
usually used for instruction memory. The ucs_n defaults to an active state at reset with a
memory range of 64 Kbytes (F0000h to FFFFFh), external ready required, and three wait states
automatically inserted. The upper end of the memory range always ends at FFFFFh. The lower
end of this upper memory range is programmable. The value of the UMCS register is F03Bh at
reset (see Table 36).
Table 36. Upper-Memory Chip Select Register
15 14 13 12 11 10
LB2–LB0
9
0
8
0
7
DA
6
0
5
1
4
1
3
1
2
1
0
1
0
0
R2 R1–R0
Bit [15]—Reserved. Set to 1.
Bits [14–12]—LB [2–0] → Lower Boundary. These bits determine the bottom of the
memory accessed by the ucs_n chip selects. The UMCS Block-Size Programming Values
shown below list the possible block-size configurations (a 512-Kbyte maximum).
UMCS Block-Size Programming Values
Memory
Starting
Block Size Address LB2–LB0 Comments
64K
F0000h
E0000h
C0000h
80000h
111b
110b
100b
000b
Default
128K
256K
512K
–
–
–
Bits [11–8]—Reserved. Set to 0.
Bit [7]—DA Disable Address → When set to 1, the address bus is disabled and the
address is not driven on the address bus when ucs_n is asserted, providing some measure
of power saving. When 0, the address is driven onto the address bus (ad15–ad0) during
the address phase of a bus cycle when ucs_n is asserted. This bit is set to 0 at reset.
– If bhe_n/aden_n is held at 0 during the rising edge of res_n, the address bus is always
driven, regardless of the setting of DA.
Bit [6]—Reserved. Set to 0.
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