IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
Table 37. Baud Rates
Divisor Based on CPU Clock Rate
Baud Rate 20 MHz 25 MHz 33 MHz 40 MHz
300
600
1050
1200
1800
2400
4800
7200
4166
2083
1190
1041
694
520
260
173
130
65
43
33
22
22
16
10
9
8
5208
2604
1488
1302
868
651
325
217
162
81
54
40
28
27
20
13
12
10
6875
3437
1964
1718
1145
859
429
286
214
107
71
53
36
35
26
18
16
13
8333
4166
2380
2083
1388
1041
520
347
260
130
86
65
45
43
32
22
19
16
9600
19200
28800
38400
56000
57600
76800
115200
128000
153600
Special
187500
15 MHz 21 MHz 24 MHz 30 MHz
10
5
7
8
The value of the SP0BAUD and SP1BAUD registers at reset is 0000h (see Table 38).
Table 38. Serial Port Baud Rate Divisor Registers
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
BAUDDIV
Bits [15–0]—BAUDDIV Baud Rate Divisor → Defines the divisor for the internal
processor clock.
5.1.23 SP0RD (086h) and SP1RD (016h)
Serial Port Receive Registers. Data received over the serial ports are stored in these registers
until read. The data are received initially by the receive shift register (no software access)
permitting data to be received while the previous data are being read.
The status of these registers is indicated by the RDR bit (Receive Data Ready) in the serial port
status registers. Setting the RDR bit to 1 indicates that there is valid data in the receive register.
The RDR bit is cleared automatically when the receive register is read.
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