IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
5.1.17 MMCS (0a6h)
Midrange Memory Chip Select (MMCS) Register. Four chip-select pins, mcs3_n–mcs0_n, are
provided for use within a user-locatable memory block. Excluding the areas associated with the
ucs_n and lcs_n chip selects (and if mapped to memory, the address range of the peripheral chip
selects, pcs6_n–pcs5_n and pcs3_n–pcs0_n), the memory block base address can be located
anywhere within the 1-Mbyte memory address space. If the pcs_n chip selects are mapped to
I/O space, the mcs_n address range can overlap the pcs_n address range.
Two registers program the Midrange Chip Selects. The MMCS register determines the base
address, the ready condition, and wait states of the memory block that are accessed through the
mcs_n pins. The pcs_n and mcs_n auxiliary (MPCS) register configures the block size. On
reset, the mcs3_n–mcs0_n pins are not active. Accessing with a write both the MMCS and
MPCS registers activate these chip selects.
Unlike the ucs_n and lcs_n chip selects, the mcs3_n–mcs0_n outputs assert with the multiplexed
ad address bus (ad15–ad0 or ao15–ao8 and ad7–ad0), rather than the earlier timing of the a19–a0
bus. If the a19–a0 bus is used for address selection, the timing is delayed for a half cycle later
than that for ucs_n and lcs_n. The value is undefined at reset (see Table 33).
Table 33. Midrange Memory Chip Select Register
15 14 13 12 11 10
9
8
1
7
1
6
1
5
1
4
1
3
1
2
1
0
BA19–BA13
R2 R1–R0
Bits [15–9]—BA [15–9] Base Address → The value of the BA19–BA13 determines the
base address of the memory block that is addressed by the mcs_n chip select pins. These
bits correspond to a19–a13 of the 20-bit memory address. The remaining bits a12–a0 of
the base address are always 0.
– The base address may be any integer multiple of the size of the memory clock
selected in the MPCS register. For example, if the midrange block is 32 Kbytes, the
block could be located at 20000h or 28000h but not at 24000h.
– If the lcs_n chip select is inactive, the base address of the midrange chip selects can
be set to 00000h, because the lcs_n chip select is defined to be 00000h but is unused.
Because the base address must be an integer multiple of the block size, a 512K
MMCS block size can only be used with the lcs_n chip select inactive and the base
address of the midrange chip selects set to 00000h.
Bits [8–3]—Reserved. Set to 1.
Bit [2]—R2 Ready mode → This bit determines the mcs_n chip selects ready mode.
When set to 1, an external ready is ignored. When 0, an external ready is necessary. Its
value determines the number of wait states inserted into an access.
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