IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
Bit [15]—DM/IOn → Destination Address Space Select selects memory or I/O space for
the destination address. When DM/IO is set to 1, the destination address is in memory
space. When 0, it is in I/O space.
Bit [14]—DDEC → Destination Decrement when set to 1, automatically decrements the
destination address after each transfer. The address is decremented by 1 or 2, depending
on the byte/word bit (Bn/W, Bit [0]). The address does not change if the increment and
decrement bits are set to the same value (00b or 11b).
Bit [13]—DINC → Destination Increment when set to 1, automatically increments the
destination address after each transfer. The address is incremented by 1 or 2, depending
on the byte/word bit (Bn/W, Bit [0]). The address does not change if the increment and
decrement bits are set to the same value (00b or 11b).
Bit [12]—SM/IOn → Source Address Space Select selects memory or I/O space for the
source address. When set to 1, the source address is in memory space. When 0, it is in
I/O space.
Bit [11]—SDEC → Source Decrement when set to 1, automatically decrements the
destination address after each transfer. The address is decremented by 1 or 2, depending
on the byte/word bit (Bn/W, Bit [0]). The address does not change if the increment and
decrement bits are set to the same value (00b or 11b).
Bit [10]—SINC → Source Increment when set to 1, automatically increments the
destination address after each transfer. The address is incremented by 1 or 2, depending
on the byte/word bit (Bn/W, Bit [0]). The address does not change if the increment and
decrement bits are set to the same value (00b or 11b).
Bit [9]—TC → Terminal Count. The DMA decrements the transfer count for each DMA
transfer. When set to 1, the source or destination synchronized DMA transfers terminate
when the count reaches 0. When 0, they do not terminate when the count reaches 0.
Unsynchronized DMA transfers always end when the count reaches 0, regardless of the
setting of this bit.
Bit [8]—INT → Interrupt. When this bit is set to 1, the DMA channel generates an
interrupt request on completion of the transfer count. However, for an interrupt to be
generated, the TC bit must also be set to 1.
Bits [7–6]—SYN1–SYN0 → Synchronization Type bits each select channel
synchronization types as shown below. The value of these bits is ignored if TDRQ
(Bit [4]) is set to 1. A processor reset causes these bits to be set to 11b.
®
IA211050902-19
UNCONTROLLED WHEN PRINTED OR COPIED
http://www.innovasic.com
Customer Support:
Page 70 of 154
1-888-824-4184
INNOVASIC [ INNOVASIC, INC ]
