IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
Bit [1]—MSIZ (IA186ES only) → When set to 1, 8-bit data accesses are performed in
middle chip-select (mcs_n) space and peripheral chip-select space (psc_n—but only if
pcs_n is mapped to memory). When 0, 16-bit data accesses are performed.
Bit [0]—IOSIZ (IA186ES only) → When set to 1, 8-bit data accesses are performed in all
I/O space. When 0, 16-bit data accesses are performed.
5.1.5 SYSCON (0f0h)
The SYStem CONfiguration Register controls several miscellaneous system I/O and timing
functions. The SYSCON contains 0000h at reset (see Table 21).
Table 21. System Configuration Register
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PSEN MCSBIT DSDEN PWD CBF CBD CAF CAD
RES
F2 F1 F0
Bit [15]—PSEN → When set to 1, enables the power-save mode causing the internal
operating clock to be divided by the value in F2–F0. External or internal interrupts clear
PSEN automatically. Software interrupts and exceptions do not.
Note: The value of PSEN is not restored upon execution of an IRET
instruction.
Bit [14]—MCSBIT → When set to 1, mcs0_n is active over the entire MCS range, thus
freeing msc2 _n and mcs1_n to be used as PIO. When 0, it behaves normally.
Bit [13]—DSDEN → When set to 1, the ds_n/den_n pin functions as ds_n. When 0, it
functions as den_n. See the individual pin descriptions for details of data strobe (ds_n)
mode versus data enable (den_n) mode.
Bit [12]—PWD → When set to 1, the pulse width demodulator is enabled. When 0, it is
disabled.
Bit [11]—CBF → When set to 1, the clkoutb output follows the input crystal (PLL)
frequency. When 0, it follows the internal clock frequency after the clock divider.
Bit [10]—CBD → When set to 1, the clkoutb output is driven low. When 0, it is driven
as an output per the CBF bit.
Bit [9]—CAF → When set to 1, the clkouta output follows the input crystal (PLL)
frequency. When 0, it follows the internal clock frequency after the clock divider.
®
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