IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
Table 41. Serial Port Status Register ............................................................................................83
Table 42. Serial Port Control Registers ........................................................................................84
Table 43. PIO Pin Assignments....................................................................................................88
Table 44. PDATA 0......................................................................................................................89
Table 45. PDATA 1......................................................................................................................89
Table 46. PIO Mode and PIO Direction Settings .........................................................................89
Table 47. PDIR0 ...........................................................................................................................90
Table 48. PDIR1 ...........................................................................................................................90
Table 49. PMODE0 ......................................................................................................................90
Table 50. PMODE1 ......................................................................................................................90
Table 51. Timer0 and Timer1 Mode and Control Registers.........................................................91
Table 52. Timer2 Mode and Control Registers ............................................................................92
Table 53. Timer Maxcount Compare Registers............................................................................93
Table 54. Timer Count Registers..................................................................................................94
Table 55. Serial Port Interrupt Control Registers .........................................................................94
Table 56. INT4 Control Register ..................................................................................................95
Table 57. INT2/INT3 Control Register ........................................................................................96
Table 58. INT0/INT1 Control Register ........................................................................................96
Table 59. Timer Control Unit Interrupt Control Register.............................................................97
Table 60. Timer Interrupt Control Register..................................................................................97
Table 61. DMA and Interrupt Control Register (Master Mode)...................................................98
Table 62. DMA and Interrupt Control Register (Slave Mode).....................................................98
Table 63. Interrupt Status Register (Master Mode) ......................................................................99
Table 64. Interrupt Status Register (Slave Mode) ........................................................................99
Table 65. Interrupt Request Register (Master Mode).................................................................100
Table 66. Interrupt Request Register (Slave Mode) ...................................................................101
Table 67. In-Service Register (Master Mode) ............................................................................102
Table 68. In-Service Register (Slave Mode)...............................................................................102
Table 69. Priority Mask Register................................................................................................103
Table 70. Interrupt MASK Register (Master Mode) ..................................................................104
Table 71. Interrupt MASK Register (Slave Mode).....................................................................104
Table 72. POLL Status Register .................................................................................................105
Table 73. Poll Register................................................................................................................106
Table 74. End-Of-Interrupt Register...........................................................................................106
Table 75. Specific End-Of-Interrupt Register.............................................................................106
Table 76. Interrupt Vector Register ............................................................................................107
Table 77. Alphabetic Key to Waveform Parameters ..................................................................108
Table 78. Numeric Key to Waveform Parameters......................................................................110
Table 79. Read Cycle Timing.....................................................................................................115
Table 80. Write Cycle Timing ....................................................................................................118
Table 81. PSRAM Read Cycle Timing.......................................................................................120
Table 82. PSRAM Write Cycle Timing......................................................................................122
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