IA186ES/IA188ES
Data Sheet
8-Bit/16-Bit Microcontrollers
November 15, 2011
LIST OF TABLES
Table 1. IA186ES TQFP Numeric Pin Listing .............................................................................18
Table 2. IA186ES TQFP Alphabetic Pin Listing..........................................................................19
Table 3. IA188ES TQFP Numeric Pin Listing .............................................................................21
Table 4. IA188ES TQFP Alphabetic Pin Listing..........................................................................22
Table 5. IA186ES PQFP Numeric Pin Listing .............................................................................25
Table 6. IA186ES PQFP Alphabetic Pin Listing..........................................................................26
Table 7. IA188ES PQFP Numeric Pin Listing .............................................................................28
Table 8. IA188ES PQFP Alphabetic Pin Listing..........................................................................29
Table 9. Bus Cycle Types for bhe_n and ad0...............................................................................32
Table 10. Bus Cycle Types for s2_n, s1_n, and s0_n...................................................................42
Table 11. IA186ES and IA188ES Absolute Maximum Ratings...................................................45
Table 12. IA186ES and IA188ES Thermal Characteristics..........................................................45
Table 13. DC Characteristics Over Commercial Operating Ranges.............................................46
Table 14. Interrupt Types..............................................................................................................54
Table 15. Default Status of PIO Pins at Reset ..............................................................................61
Table 16. Peripheral Control Registers.........................................................................................63
Table 17. Peripheral Control Block Relocation Register..............................................................64
Table 18. Reset Configuration Register........................................................................................64
Table 19. Processor Release Level Register.................................................................................65
Table 20. Auxiliary Configuration Register .................................................................................65
Table 21. System Configuration Register.....................................................................................66
Table 22. Watchdog Timer Control Register................................................................................67
Table 23. Enable Dynamic RAM Refresh Control Register.........................................................68
Table 24. Count for Dynamic RAM Refresh Control Register ....................................................69
Table 25. Memory Partition for Dynamic RAM Refresh Control Register .................................69
Table 26. DMA Control Registers................................................................................................69
Table 27. DMA Transfer Count Registers....................................................................................71
Table 28. DMA Destination Address High Register ....................................................................72
Table 29. DMA Destination Address Low Register.....................................................................72
Table 30. DMA Source Address High Register............................................................................73
Table 31. DMA Source Address Low Register ............................................................................73
Table 32. MCS and PCS Auxiliary Register ................................................................................74
Table 33. Midrange Memory Chip Select Register ......................................................................75
Table 34. Peripheral Chip Select Register....................................................................................76
Table 35. Low-Memory Chip Select Register..............................................................................78
Table 36. Upper-Memory Chip Select Register ...........................................................................79
Table 37. Baud Rates ....................................................................................................................81
Table 38. Serial Port Baud Rate Divisor Registers.......................................................................81
Table 39. Serial Port Receive Registers........................................................................................82
Table 40. Serial Port Transmit Registers ......................................................................................82
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