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AM186EM-25VIW 参数 Datasheet PDF下载

AM186EM-25VIW图片预览
型号: AM186EM-25VIW
PDF下载: 下载PDF文件 查看货源
内容描述: 8位/ 16位微控制器 [8-Bit/16-Bit Microcontrollers]
分类和应用: 微控制器
文件页数/大小: 146 页 / 1574 K
品牌: INNOVASIC [ INNOVASIC, INC ]
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IA186EM/IA188EM  
Data Sheet  
8-Bit/16-Bit Microcontrollers  
February 25, 2011  
The value of the PIOMODE1 register is 0000h at reset (see Table 48).  
Table 48. PMODE1  
15 14 13 12 11 10  
9
8
7
6
5
4
3
2
1
0
PMODE31PMODE16  
Bits [150]PMODE15PMODE0 PIO Mode 0 Bits For each bit, if the value is 1,  
the pin is configured as an input. If 0, an output. The values of these bits correspond to  
those in the PIO data registers and PIO Mode registers.  
Bits [150]PMODE31PMODE16 PIO Mode 1 Bits For each bit, if the value is 1,  
the pin is configured as an input. If 0, an output. The values of these bits correspond to  
those in the PIO data registers and PIO Mode registers.  
5.1.27 T1CON (05eh) and T0CON (056h)  
Timer 0 and Timer 1 Mode and CONtrol Registers. These registers control the operation of  
Timer 0 and Timer 1, respectively. The value of the T0CON and T1CON registers is 0000h at  
reset (see Table 49).  
Table 49. Timer 0 and Timer 1 Mode and Control Registers  
15  
14  
13  
12 11 10  
9
8
7
6
5
4
3
2
1
0
EN INHn INT RIU  
Reserved  
MC RTG  
P
EXT ALT CONT  
Bit [15]EN Enable Bit The timer is enabled when the EN bit is 1. The timer count  
is inhibited when the EN bit is 0. This bit is write-only and can only be written if the  
INHn bit (Bit [14]) is set to 1 in the same operation.  
Bit [14]INHn Inhibit Bit Gates the setting of the enable (EN) bit. This bit must be  
set to 1 in the same write operation that sets the enable (EN) bit. Otherwise, the EN bit  
will not be changed. This bit always reads 0.  
Bit [13]INT Interrupt Bit An interrupt request is generated when the Count register  
reaches its maximum, MC = 1, by setting the INT bit to 1. In dual maxcount mode, an  
interrupt request is generated when the count register reaches the value in Maxcount A or  
Maxcount B. No interrupt requests are generated if this bit is set to 0. If an interrupt  
request is generated, and the enable bit is then cleared before the interrupt is serviced, the  
interrupt request will remain.  
Bit [12]RIU Register in Use Bit This bit is set to 1 when the Maxcount Register B is  
used to compare to the timer-count value. It is 0 when the Maxcount Compare A register  
is used.  
®
IA211050831-19  
UNCONTROLLED WHEN PRINTED OR COPIED  
http://www.Innovasic.com  
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