IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
Bit [8]—CAD → When set to 1, the clkouta output is pulled low. When 0, it is driven as
an output per the CBF bit.
Bits [7–3]—Reserved → These bits read back as 0.
Bits [2–0]—F2–F0 → These bits control the clock divider as shown below.
Note: PSEN must be 1 for the clock divider to function.
F2 F1 F0 Divider Factor
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Divide by 1 (20)
Divide by 2 (21)
Divide by 4 (22)
Divide by 8 (23)
Divide by 16 (24)
Divide by 32 (25)
Divide by 64 (26)
Divide by 128 (27)
5.1.5 EDRAM (0e4h)
The Enable RCU Register provides control and status for the refresh counter. The EDRAM
register contains 0000h at reset (see Table 21).
Table 21. Enable Dynamic RAM Refresh Control Register
15 14 13 12 11 10
Reserved
9
8
7
6
5
4
3
2
1
0
E
T8–T0
Bit [15]—E → When set to 1, the refresh counter is enabled and msc3_n is configured to
act as rfsh_n. Clearing E empties the refresh counter and disables refresh requests. The
refresh address is unaffected by clearing E.
Bits [14–9]—Reserved → These bits read back as 0.
Bits [8–0]—T8–T0 → These bits hold the current value of the refresh counter. They are
read-only.
5.1.6 CDRAM (0e2h)
The Clock Prescaler Register determines the period between refresh cycles. The Count for
Dynamic RAM (CDRAM) register is undefined at reset (see Table 22).
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