IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
Table 19. Processor Release Level Register
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
PRL7–PRL0
Reserved
Bits [15–8]—PRL7–PRL0 → The latest Processor Release Level.
Processor
PRL Value Release Level
01h
02h
03h
04h
C
D
E
F
Bits [7–0]—Reserved.
5.1.4 PDCON (0f0h)
The Power-save CONtrol Register controls several miscellaneous system I/O and timing
functions. The PDCON contains 0000h at reset (see Table 20).
Table 20. Power-Save Control Register
15
PSEN
14 13 12
Reserved
11
10
9
8
7
6
5
4
3
2
1
0
CBF CBD CAF CAD
Reserved
F2 F1 F0
Bit [15]—PSEN → When set to 1, enables the power-save mode causing the internal
operating clock to be divided by the value in F2–F0. External interrupts or interrupts
from internal interrupts automatically clear PSEN. Software interrupts and exception do
not clear PSEN.
Note: The value of PSEN is not restored upon execution of an IRET
instruction.
Bits [14–12]—Reserved → These bits read back as 0.
Bit [11]—CBF → When set to 1, the clkoutb output follows the input crystal (PLL)
frequency. When 0, it follows the internal clock frequency after the clock divider.
Bit [10]—CBD → When set to 1, the clkoutb output is pulled low. When 0, it is driven
as an output per the CBF bit.
Bit [9]—CAF → When set to 1, the clkouta output follows the input crystal (PLL)
frequency. When 0, it follows the internal clock frequency after the clock divider.
®
IA211050831-19
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