IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
Table 86. PSRAM Write Cycle Timing
a
a
No.
Name
Comment
Min
Max
General Timing Requirements
1
2
tDVCL
tCLDX
Data in Setup
Data in Hold
10
0
–
–
General Timing Responses
5
7
8
9
tCLAV
tCLDV
tCHDX
tCHLH
ad Address Valid Delay
Data Valid Delay
Status Hold Time
ale Active Delay
ale Width
0
0
0
0
12
12
–
8
10 tLHLL
11 tCHLL
tCLCH-5
–
ale Inactive Delay
NULL
NULL
20 tCVCTV Control Active Delay 1
23 tLHAV ale High to Address Valid
0
10
–
7.5
80 tCLCLX lcs_n Inactive Delay
81 tCLCSL lcs_n Active Delay
0
9
0
9
84 tLRLL
lcs_n Precharge Pulse Width
tCLCL+ tCLCH
–
Write Cycle Timing Responses
30 tCLDOX Data Hold Time
31 tCVCTX Control Inactive Delay
32 tWLWH wr_n Pulse Width
0
0
–
10
–
2tCLCL
tCLCH
tCLCL
33 tWHLH
34 tWHDX
65 tAVWL
68 tCHAV
87 tAVBL
wr_n Inactive to ale High
–
Data Hold after wr_n
–
a Address Valid to wr_n Low
clkouta High to a Address Valid
a Address Valid to whb_n/wlb_n Low
tCLCL+ tCHCL
0
–
8
tCHCL -1.5
–
a
In nanoseconds.
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