IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
Table 85. PSRAM Read Cycle Timing
a
a
No.
Name
Comment
Min
Max
General Timing Requirements
1
2
tDVCL
tCLDX
Data in Setup
Data in Hold
10
0
NLL
–
General Timing Responses
5
tCLAV
tCLDV
tCHDX
tCHLH
tLHLL
tCHLL
tLHAV
ad Address Valid Delay
Data Valid Delay
Status Hold Time
ale Active Delay
0
0
0
0
12
12
–
7
8
9
8
10
11
23
80
81
84
ale Width
tCHCL-5
–
ale Inactive Delay
ale High to Address Valid
0
8
7.5
–
tCLCLX lcs_n Inactive Delay
tCLCSL lcs_n Active Delay
0
9
0
9
tLRLL
lcs_n Precharge Pulse Width
tCLCL+ tCLCH
–
Read Cycle Timing Responses
24
25
26
27
28
59
66
68
tAZRL
tCLRL
tRLRH
tCLRH
tRHLH
tRHDX
tAVRL
tCHAV
ad Address Float to rd_n Active
rd_n Active Delay
0
–
10
–
0
rd_n Pulse Width
tCLCL
rd_n Inactive Delay
0
10
–
rd_n Inactive to ale High
rd_n High to Data Hold on ad Bus
a Address Valid to rd_n Low
clkouta High to a Address Valid
tCLCH
0
–
tCLCL+ tCHCL
0
–
8
a
In nanoseconds.
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