IA186EM/IA188EM
Data Sheet
8-Bit/16-Bit Microcontrollers
February 25, 2011
Table 84. Write Cycle Timing
a
a
No.
Name
Description
Min
Max
General Timing Requirements
1
2
tDVCL
tCLDX
Data in Setup
Data in Hold
10
0
–
–
General Timing Responses
3
tCHSV
tCLSH
tCLAV
tCLAX
tCLDV
tCHDX
tCHLH
tLHLL
Status Active Delay
Status Inactive Delay
ad Address Valid Delay
Address Hold
0
0
0
0
0
0
0
6
6
4
5
12
12
12
–
6
7
Data Valid Delay
Status Hold Time
ale Active Delay
ale Width
8
9
8
10
11
12
13
14
16
17
18
19
20
22
23
tCLCH-5
–
tCHLL
tAVLL
ale Inactive Delay
0
8
ad Address Valid to ale Low
ad Address Hold from ale Inactive
ad Address Valid to Clock High
mcs_n/pcs_n Inactive Delay
mcs_n/pcs_n Hold from Command Inactive
mcs_n/pcs_n Inactive Delay
den_n Inactive to dt/r_n Low
Control Active Delay 1
tCLCH
–
tLLAX
tCHCL
–
tAVCH
tCLCSV
tCXCSX
tCHCSX
tDXDL
tCVCTV
tCHCTV
tLHAV
0
–
0
12
–
tCLCH
0
0
12
–
0
10
9
Control Active Delay 2
0
ale High to Address Valid
7.5
–
Write Cycle Timing Responses
30
31
32
33
34
35
65
67
68
87
tCLDOX
tCVCTX
tWLWH
tWHLH
tWHDX
Data Hold Time
0
–
10
–
Control Inactive Delay
wr_n Pulse Width
0
2tCLCL
tCLCH
tCLCL
wr_n Inactive to ale High
Data Hold after wr_n
–
–
tWHDEX wr_n Inactive to den_n Inactive
tCLCH
tCLCL + tCHCL
0
–
tAVWL
tCHCSV
tCHAV
tAVBL
a Address Valid to wr_n Low
–
clkouta High to lcs_n/usc_n Valid
clkouta High to a Address Valid
a Address Valid to whb_n/wlb_n Low
9
0
8
tCHCL -1.5
–
a
In nanoseconds.
®
IA211050831-19
UNCONTROLLED WHEN PRINTED OR COPIED
http://www.Innovasic.com
Customer Support:
Page 111 of 146
1-888-824-4184
INNOVASIC [ INNOVASIC, INC ]
