XMC4500
XMC4000 Family
Electrical Parameters
3.3.4
Phase Locked Loop (PLL) Characteristics
Note: These parameters are not subject to production test, but verified by design and/or
characterization.
Main and USB PLL
Table 34
PLL Parameters
Parameter
Symbol
Values
Typ.
−
Unit Note /
Test Condition
Min.
Max.
Accumulated Jitter
Duty Cycle1)
DP CC
−
±5
ns
accumulated
over 300 cycles
f
SYS = 120 MHz
DDC CC 46
50
54
%
Low pulse to
total period,
assuming an
ideal input clock
source
PLL base frequency
fPLLBASE 30
−
140
MHz
CC
VCO input frequency
VCO frequency range
PLL lock-in time
f
f
REF CC
4
−
−
−
16
MHz
MHz
μs
VCO CC 260
520
400
tL CC
−
1) 50% for even K2 divider values, 50±(10/K2) for odd K2 divider values.
Data Sheet
65
V1.0, 2013-01
Subject to Agreement on the Use of Product Information
INFINEON [ Infineon ]
