XC2287 / XC2286 / XC2285
XC2000 Family Derivatives
Preliminary
Functional Description
3.13
Watchdog Timer
The Watchdog Timer represents one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Watchdog Timer is always enabled after a reset of the chip, and can be disabled
and enabled at any time by executing instructions DISWDT and ENWDT. Thus, the
chip’s start-up procedure is always monitored. The software has to be designed to
service the Watchdog Timer before it overflows. If, due to hardware or software related
failures, the software fails to do so, the Watchdog Timer overflows and generates a
prewarning interrupt and then a reset request.
The Watchdog Timer is a 16-bit timer, clocked with the system clock divided by 16,384
or 256. The Watchdog Timer register is set to a prespecified reload value (stored in
WDTREL) in order to allow further variation of the monitored time interval. Each time it
is serviced by the application software, the Watchdog Timer is reloaded and the
prescaler is cleared.
Thus, time intervals between 3.9 µs and 16.3 s can be monitored (@ 66 MHz).
The default Watchdog Timer interval after power-up is 6.5 ms (@ 10 MHz).
Data Sheet
64
V0.91, 2007-02
Draft Version
INFINEON [ Infineon ]
