TLE9879QXA40
DMA Controller
9
DMA Controller
Figure 13 shows the Top Level Block Diagram of the TLE9879QXA40.
The bus matrix allows the uDMA to access the PBA0, PBA1 and RAM.
9.1
Features
The principal features of the DMA Controller are that:
•
•
•
•
•
•
•
it is compatible with AHB-Lite for the DMA transfers
it is compatible with APB for programming the registers
it has a single AHB-Lite master for transferring data using a 32-bit address bus and 32-bit data bus
it supports 13 DMA channels
each DMA channel has dedicated handshake signals
each DMA channel has a programmable priority level
each priority level arbitrates using a fixed priority that is determined by the DMA channel number. The DMA
also supports multiple transfer types:
- memory-to-memory
- memory-to-peripheral
- peripheral-to-memory
•
•
•
•
•
it supports multiple DMA cycle types
it supports multiple DMA transfer data widths
each DMA channel can access a primary, and alternate, channel control data structure
all the channel control data is stored in system memory (RAM) in little-endian format
it performs all DMA transfers using the SINGLE AHB-Lite burst type. The destination data width is equal to the
source data width.
•
•
the number of transfers in a single DMA cycle can be programmed from 1 to 1024
the transfer address increment can be greater than the data width
Data Sheet
34
Rev. 1.0, 2015-04-30
INFINEON [ Infineon ]
