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TLE9879QXA40 参数 Datasheet PDF下载

TLE9879QXA40图片预览
型号: TLE9879QXA40
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller with LIN and BLDC MOSFET Driver for Automotive Applications]
分类和应用: 微控制器
文件页数/大小: 122 页 / 4340 K
品牌: INFINEON [ Infineon ]
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TLE9879QXA40  
ARM Cortex M3 Core  
8
ARM Cortex M3 Core  
8.1  
Features  
The key features of the Cortex M3 implemented are listed below.  
Processor Core. A low gate count core, with low latency interrupt processing:  
A subset of the Thumb®-2 Instruction Set  
Banked stack pointer (SP) only  
32-bit hardware divide instructions, SDIV and UDIV (Thumb-2 instructions)  
Handler and Thread Modes  
Thumb and debug states  
Interruptible-continued instructions LDM/STM, Push/Pop for low interrupt latency  
Automatic processor state saving and restoration for low latency Interrupt Service Routine (ISR) entry and exit  
ARM architecture v7-M Style BE8/LE support  
ARMv6 unaligned accesses  
Nested Vectored Interrupt Controller (NVIC) closely integrated with the processor core to achieve low  
latency interrupt processing:  
Interrupts, configurable from 1 to 16  
Bits of priority (4)  
Dynamic reprioritization of interrupts  
Priority grouping. This enables selection of preemptive interrupt levels and non-preemptive interrupt levels  
Support for tail-chaining and late arrival of interrupts. This enables back-to-back interrupt processing without  
the overhead of state saving and restoration between interrupts.  
Processor state automatically saved on interrupt entry, and restored on interrupt exit, with no instruction  
overhead  
Bus interfaces  
Advanced High-performance Bus-Lite (AHB-Lite) interfaces: ICode, DCode, and System bus interface  
Memory access alignment  
Write buffer for buffering of write data  
8.2  
Introduction  
The ARM Cortex-M3 processor is a leading 32-bit processor and provides a high-performance and cost-optimized  
platform for a broad range of applications including microcontrollers, automotive body systems and industrial  
control systems. Like the other Cortex family processors, the Cortex-M3 processor implements the Thumb®-2  
instruction set architecture. With the optimized feature set the Cortex-M3 delivers 32-bit performance in an  
application space that is usually associated with 8- and 16-bit microcontrollers.  
Data Sheet  
32  
Rev. 1.0, 2015-04-30  
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