TLE9879QXA40
Power Management Unit (PMU)
5
Power Management Unit (PMU)
5.1
Features
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System modes control (startup, sleep, stop and active)
Power management (cyclic wake-up)
Control of system voltage regulators with diagnosis (overload, short, over-voltage)
Fail safe mode detection and operation in case of system errors (watchdog fail)
Wake-up sources configuration and management (LIN, MON, GPIOs)
System error logging
5.2
Introduction
The power management unit is responsible for generating all required voltage supplies for the embedded MCU
(VDDC, VDDP) and the external supply (VDDEXT). The power management unit is designed to ensure fail-safe
behavior of the system IC by controlling all system modes including the corresponding transitions. Additionally, the
PMU provides well defined sequences for the system mode transitions and generates hierarchical reset priorities.
The reset priorities control the reset behavior of all system functionalities especially the reset behavior of the
embedded MCU. All these functions are controlled by a state machine. The system master functionality of the
PMU make use of an independent logic supply and system clock. For this reason, the PMU has an "Internal logic
supply and system clock" module which works independently of the MCU clock.
Data Sheet
18
Rev. 1.0, 2015-04-30
INFINEON [ Infineon ]
