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    TLD7002-16ES 参数 Datasheet PDF下载

    TLD7002-16ES图片预览
    型号： TLD7002-16ES
    PDF下载： 下载PDF文件 查看货源
    内容描述： [The TLD7002-16ES is a 16 channel device with integrated and protected output stages. It is designed to control LEDs with a current up to 76.5 mA as linear current sink (LCS). The power stages can be configured in parallel for higher load currents. Each individual power output stage is configured to a 6-bit current set value stored in the OTP. 16 independent and individual PWM configurations can be set. A high-speed lighting interface is used for device OTP programming, configuration, control and]
    分类和应用：
    文件页数/大小： 82 页 / 3105 K
    品牌： INFINEON [ Infineon ]
     浏览型号TLD7002-16ES的Datasheet PDF文件第44页浏览型号TLD7002-16ES的Datasheet PDF文件第45页浏览型号TLD7002-16ES的Datasheet PDF文件第46页浏览型号TLD7002-16ES的Datasheet PDF文件第47页浏览型号TLD7002-16ES的Datasheet PDF文件第49页浏览型号TLD7002-16ES的Datasheet PDF文件第50页浏览型号TLD7002-16ES的Datasheet PDF文件第51页浏览型号TLD7002-16ES的Datasheet PDF文件第52页  
    TLD7002-16ES  
    Datasheet  
    9 Communication interface  
    Table 26  
    HSLI interframe delay  
    Step  
    tframedly  
    50 µs  
    0
    1
    100 µs  
    250 µs  
    500 µs  
    1 ms  
    2
    3
    4 (default)  
    5
    2.5 ms  
    The device starts counting the interframe delay from the last received dominant bit and not at the end of the byte  
    transmitted.  
    In case of a 0xFF byte transmission the counting starts from the start bit.  
    9.1.5  
    Slave response bus idle time  
    The slave responds to a valid master request within tbus_idle when requested by the master.  
    9.1.6  
    UART byte field  
    The next figure shows the standard UART byte field. This structure is the basis for data transfer between slave and  
    master. The LSB of the data is transmitted first and the MSB last. The start bit is encoded as a low and the stop bit is  
    encoded as a high bit.  
    Figure 18  
    UART byte field  
    9.1.7  
    HSLI baud rate auto detection  
    The HSLI supports Baud rates in the range of nBaud. The Baud rate configuration is automatically detected based on  
    the master request.  
    9.1.8  
    HSLI bit timing  
    The HSLI uses a variable oversampling for the RX signal within 16 quanta with a configurable bit sample timing stored  
    in the OTP.  
    Table 27  
    HSLI bit timing  
    Step  
    nBST  
    0 (default)  
    7,8,9  
    1
    2
    3
    8,9,10  
    9,10,11  
    10,11,12  
    Datasheet  
    48  
    Rev.1.00  
    2022-05-03  

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