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SAK-TC399XP-256F300S BC 参数 Datasheet PDF下载

SAK-TC399XP-256F300S BC图片预览
型号: SAK-TC399XP-256F300S BC
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内容描述: [Infineon releases its second generation AURIX microcontroller in embedded flash 40 nm technology. It comes back with an increase in performance, memory sizes, connectivity and more scalability to address the new automotive trends and challenges. This family has more than 20 products to provide the most scalable portfolio of safety microcontrol­ler. In terms of performance, the highest end product TC39x offers 6 cores running at 300 MHz and up to 6.9 MBytes embedded RAM, and consuming below 2 W. ]
分类和应用:
文件页数/大小: 548 页 / 21256 K
品牌: INFINEON [ Infineon ]
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TC39x BC/BD-Step  
Summary of Features  
1
Summary of Features  
The TC39x product family has the following features:  
High Performance Microcontroller with six CPU cores  
Six 32-bit super-scalar TriCore CPUs (TC1.6.2P), each having the following features:  
Superior real-time performance  
Strong bit handling  
Fully integrated DSP capabilities  
Multiply-accumulate unit able to sustain 2 MAC operations per cycle  
Fully pipelined Floating point unit (FPU)  
up to 300 MHz operation at full temperature range  
up to 240/96 Kbyte Data Scratch-Pad RAM (DSPR)  
up to 64 Kbyte Instruction Scratch-Pad RAM (PSPR)  
up to 64 Kbyte Data RAM (DLMU)  
32 Kbyte Instruction Cache (ICACHE)  
16 Kbyte Data Cache (DCACHE)  
Lockstepped shadow cores for four TC1.6.2P  
Multiple on-chip memories  
All embedded NVM and SRAM are ECC protected  
up to 16 Mbyte Program Flash Memory (PFLASH)  
up to 1 Mbyte Data Flash Memory (DFLASH 0) usable for EEPROM emulation  
768 Kbyte Memory (LMU)  
BootROM (BROM)  
128-Channel DMA Controller with safe data transfer  
Sophisticated interrupt system (ECC protected)  
High performance on-chip bus structure  
64-bit Cross Bar Interconnect (SRI) giving fast parallel access between bus masters, CPUs and memories  
32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units  
SRI to SPB bus bridges (SFI Bridge)  
Optional Hardware Security Module (HSM) on some variants  
Safety Management Unit (SMU) handling safety monitor alarms  
Memory Test Unit with ECC, Memory Initialization and MBIST functions (MTU)  
Hardware I/O Monitor (IOM) for checking of digital I/O  
Versatile On-chip Peripheral Units  
8 Asynchronous/Synchronous Serial Channels (ASCLIN) with hardware LIN support (V1.3, V2.0, V2.1 and  
J2602) up to 50 MBaud  
6 Queued SPI Interface Channels (QSPI) with master and slave capability up to 50 Mbit/s  
2 High Speed Serial Link (HSSL) for serial inter-processor communication up to 320 Mbit/s  
4 serial Micro Second Bus interfaces (MSC) for serial port expansion to external power devices  
3 MCMCAN Modules with 4 CAN nodes for high efficiency data handling via FIFO buffering  
25 Single Edge Nibble Transmission (SENT) channels for connection to sensors  
2 FlexRayTM module with 2 channels (E-Ray) supporting V2.1  
Data Sheet  
7
V 1.2, 2021-03  
OPEN MARKET VERSION  
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