TC1767
Pinning
O2 = Output with IOCR bit field selection PCx = 1X10B(ALT2)
O3 = Output with IOCR bit field selection PCx = 1X11(ALT3)
Column “Type”:
A1 = Pad class A1 (LVTTL)
A2 = Pad class A2 (LVTTL)
F = Pad class F (LVDS/CMOS)
D = Pad class D (ADC)
PU = with pull-up device connected during reset (PORST = 0)
PD = with pull-down device connected during reset (PORST = 0)
TR = tri-state during reset (PORST = 0)
3.1.2
Reset Behavior of the Pins
Table 5 describes the pull-up/pull-down behavior of the System I/O pins during power-
on reset.
Table 5
List of Pull-up/Pull-down PORST Reset Behavior of the Pins
Pins
PORST = 0
Pull-up
PORST = 1
All GPIOs, TDI, TESTMODE
PORST, TRST, TCK, TMS
ESR0
Pull-down
The open-drain driver is Pull-up2)
used to drive low.1)
ESR1
TDO
Pull-down3)
Pull-up
High-impedance
1) Valid additionally after deactivation of PORST until the internal reset phase has finished. See the SCU chapter
for details.
2) See the SCU_IOCR register description.
3) see the SCU_IOCR register description.
Data Sheet
75
V1.3, 2009-09
INFINEON [ Infineon ]
