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SAF-C167CR-LM 参数 Datasheet PDF下载

SAF-C167CR-LM图片预览
型号: SAF-C167CR-LM
PDF下载: 下载PDF文件 查看货源
内容描述: 16位CMOS单芯片微控制器 [16-Bit CMOS Single-Chip Microcontroller]
分类和应用: 微控制器和处理器外围集成电路时钟
文件页数/大小: 67 页 / 787 K
品牌: INFINEON [ Infineon ]
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C167CR  
Serial Channels  
Serial communication with other microcontrollers, processors, terminals or external peripheral  
components is provided by two serial interfaces with different functionality, an Asynchronous/  
Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC).  
ASC0 is upward compatible with the serial ports of the Siemens SAB 8051x microcontroller family  
and support full-duplex asynchronous communication up to 625 KBaud and half-duplex  
synchronous communication up to 2.5 Mbaud on the @ 20-MHz system clock.  
The SSC allows half duplex synchronous communication up to 5 Mbaud @ 20-MHz system clock.  
Two dedicated baud rate generators allow to set up all standard baud rates without oscillator tuning.  
For transmission, reception, and erroneous reception 3 separate interrupt vectors are provided for  
each serial channel.  
In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit  
and terminated by one or two stop bits. For multiprocessor communication, a mechanism to  
distinguish address from data bytes has been included (8-bit data + wake up bit mode).  
In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock  
which is generated by the ASC0. The SSC transmits or receives characters of 2...16 bits length  
synchronously to a shift clock which can be generated by the SSC (master mode) or by an external  
master (slave mode). The SSC can start shifting with the LSB or with the MSB, while the ASC0  
always shifts the LSB first.  
A loop back option is available for testing purposes.  
A number of optional hardware error detection capabilities has been included to increase the  
reliability of data transfers. A parity bit can automatically be generated on transmission or be  
checked on reception. Framing error detection allows to recognize data frames with missing stop  
bits. An overrun error will be generated, if the last character received has not been read out of the  
receive buffer register at the time the reception of a new character is complete.  
CAN-Module  
The integrated CAN-Module handles the completely autonomous transmission and reception of  
CAN frames in accordance with the CAN specification V2.0 part B (active), i.e. the on-chip CAN-  
Module can receive and transmit standard frames with 11-bit identifiers as well as extended frames  
with 29-bit identifiers.  
The module provides Full CAN functionality on up to 15 message objects. Message object 15 may  
be configured for Basic CAN functionality. Both modes provide separate masks for acceptance  
filtering which allows to accept a number of identifiers in Full CAN mode and also allows to disregard  
a number of identifiers in Basic CAN mode. All message objects can be updated independent from  
the other objects and are equipped for the maximum message length of 8 bytes.  
The bit timing is derived from the XCLK and is programmable up to a data rate of 1 MBaud. The  
CAN-Module uses two pins to interface to a bus transceiver.  
Semiconductor Group  
25  
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