C167CR
The C167CR also provides an excellent mechanism to identify and to process exceptions or error
conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate
non-maskable system reaction which is similar to a standard interrupt service (branching to a
dedicated vector table location). The occurrence of a hardware trap is additionally signified by an
individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in
progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap
services can normally not be interrupted by standard or PEC interrupts.
The following table shows all of the possible exceptions or error conditions that can arise during run-
time:
Exception Condition
Trap
Flag
Trap
Vector
Vector
Location
Trap
Number
Trap
Priority
Reset Functions:
Hardware Reset
Software Reset
Watchdog Timer Overflow
RESET
RESET
RESET
00’0000
00’0000
00’0000
00
00
00
III
III
III
H
H
H
H
H
H
Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
NMI
STKOF
STKUF
NMITRAP 00’0008
STOTRAP 00’0010
STUTRAP 00’0018
02
04
06
II
II
II
H
H
H
H
H
H
Stack Underflow
Class B Hardware Traps:
Undefined Opcode
Protected Instruction
Fault
UNDOPC BTRAP
00’0028
00’0028
0A
0A
I
I
H
H
H
H
PRTFLT
BTRAP
Illegal Word Operand
Access
ILLOPA
BTRAP
00’0028
0A
I
H
H
Illegal Instruction Access
Illegal External Bus
Access
ILLINA
ILLBUS
BTRAP
BTRAP
00’0028
00’0028
0A
0A
I
I
H
H
H
H
Reserved
[2C – 3C ] [0B – 0F ]
H H H H
Software Traps
Any
Any
Current
TRAP Instruction
[00’0000 – [00 – 7F ] CPU
H H H
00’01FC ]
Priority
H
in steps
of 4
H
Semiconductor Group
18
INFINEON [ Infineon ]
