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PEB2091NV5.3 参数 Datasheet PDF下载

PEB2091NV5.3图片预览
型号: PEB2091NV5.3
PDF下载: 下载PDF文件 查看货源
内容描述: 集成电路通信( ISDN Echocancellation电路) [ICs for Communications(ISDN Echocancellation Circuit)]
分类和应用: 电信集成电路综合业务数字网通信
文件页数/大小: 299 页 / 1531 K
品牌: INFINEON [ Infineon ]
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PEB 2091  
PEF 2091  
Functional Description  
3.6  
IOM®-2 Interface  
The IOM®-2 interface is used to interconnect telecommunication ICs. It provides a  
symmetrical full-duplex communication link, containing user data, control/programming  
and status channels. The structure used follows the 2B + 1D-channel structure of ISDN.  
The ISDN user data rate of 144 kbit/s (B1 + B2 + D) is transmitted in both directions over  
the interface.  
The IOM®-2 interface is a generalization and enhancement of the IOM®-1 interface.  
3.6.1  
IOM®-2 Frame Structure  
The IOM®-2 interface comprises two clock lines for synchronization and two data lines.  
Data is carried over Data Upstream (DU) and Data Downstream (DD) signals. The  
downstream and upstream direction are always defined with respect to the exchange.  
Downstream refers to information flow from the exchange to the subscriber and  
upstream vice versa respectively. The IOM®-2 Interface Specification describes open  
drain data lines with external pull-up resistors. However, if operation is logically  
point-to-point, tristate operation is possible as well. For IOM®-2 mode setting refer to  
"Setting Operating Modes", page 50.  
The data is clocked by a Data Clock (DCL) that operates at twice the data rate.  
Note 7:  
This is the default setting. If the microprocessor mode and the master mode  
are being used, DCL frequency can be set to the bit data rate, see "Setting  
IOM®-2 Bit Clock Mode", page 56 for details. This section will deal with the  
default setting. Nevertheless, it applies to the bit clock mode as well if DCL  
frequencies are adjusted.  
Frames are delimited by an 8-kHz Frame Synchronization Clock (FSC). Incoming data  
is sampled on every second falling edge of the DCL clock.  
Figure 23  
IOM®-2 Clocks and Data Lines  
Note 8:  
A device with an IOM®-2 interface is said to be in the ’IOM®-2 Master Mode’  
or sometimes just ’Master Mode’ if the IOM®-2 clocks FSC and DCL are  
delivered by this device. It is said to be in the ’IOM®-2 Slave Mode’ or  
sometimes just ’Slave Mode’ if the IOM®-2 Clocks are input to this device.  
Semiconductor Group  
70  
Data Sheet 01.99