PEB 2091
PEF 2091
Functional Description
Active means that the behavior is as in former versions of the IEC-Q. The IOM®-2 clocks
FSC and DCL are output on the corresponding pins.
Due to the 100 kOhm pull-up resistor this is the default configuration after reset if pin ICE
is not connected.
Table 7
Mode
Setting IOM®-2 Clock Enable/Disable Mode
Package
ADF2:ICEC bit ICE pin polarity IOM®-2
polarity
interface
P-LCC-44
Not available
Not available
Active
stand-alone mode
(PMODE= "0" or
unconnected)
M-QFP-64
or
T-QFP-64
"1" or
not connected
Not available
Active
Idle
"0"
"0"
Active
P-LCC-44
(default)
Not available
"1"
Idle
"0"
(default)
"1" or
not connected
µP mode
(PMODE="1")
M-QFP-64
or
T-QFP-64
Active
Idle
"0"
"1" or
"1"
not connected
Idle
"0"
Active
3.2.5
EOC Auto/Transparent Mode
The U-interface EOC (Embedded Operations Channel) allows transmission of
commands and informations in either direction of the U-interface. For details on EOC
structure and commands, see "Predefined EOC Codes", page 231. If the EOC
"Transparent" mode is selected EOC channel informations will be given transparently on
the IOM®-2 interface independently of the content of the EOC channel. In the EOC
"AUTO" mode an EOC processor is activated for EOC command interpretation and
handling. For operational details of the EOC in both modes see "Access to EOC of
U-Interface", page 110.
In stand-alone mode the EOC mode will be set by the input pin AUTO. In µP mode the
EOC mode will be set by bit AUTO of register STCR (see "STCR-Register", page 212).
3.2.6
Monitor Procedure Time-Out (MTO)
The IEC-Q offers an internal reset (monitor procedure "Time-out") for the monitor
procedure (see 3.6.3, page 76 for description of the IOM®-2 Monitor Channel). This reset
Semiconductor Group
55
Data Sheet 01.99
INFINEON [ Infineon ]
