PEB 2091
PEF 2091
Functional Description
Table 6
Setting DOUT Driver in µP Mode
Mode
Pin
Bit
Pin DOUT Output Driver
RES
ADF2:
Value DOUT in
DOUT in
DOD1)
activeIOM®-2 passive
Channel2)
IOM®-2
Channel
Normal
(Tristate)
1
1
0
1
0
1
0
1
low
high Z3)
high
low
Normal
floating
(Open Drain 4))
floating
1) See also "ADF2-Register", page 214
2) Refer to Notes 10, page 72, 12, page 72, and 15, page 73 for explanation about active and passive
channels
3) In TE mode bit number 27 of channel 2 (S/G bit) may be driven if the ’S/G bit control’ function is
being used (see "S/G Bit and BAC Bit Operations", page 198)
4) External pull-up resistors required (typ.1 kΩ)
IEC-Q. See Table 2, page 51. For a detailed description of the IOM®-2
interface refer to section 3.6, page 70.
Applications in which the IEC-Q is not the only potential IOM®-2 clock master on the
board have to deal with IOM®-2 clock conflicts during and after reset. Among these
applications are dual mode S- or U-terminals and circuits (see "Dual Mode U and S
Terminals and PC Cards", page 27). Typical applications would include the ISAC®-S TE
(PSB 2186) or the IPAC (PSB 2115) in TE mode. Both devices output FSC and DCL
during and after reset.
The PEB/F 2091 V5.3 in the 64 pin packages (T-QFP-64 or M-QFP-64) has a pin (pin
64, ICE) which allows to enable or disable the IOM®-2 clocks and the data-lines. It is
possible to change the status of pin ICE without the need of a reset signal being applied.
In µP mode the status of pin ICE can be overridden by bit ADF2:ICEC. Basically, the
value of pin ICE and the bit-value are EXORed (see Table 7 below).
This function can also be controlled in the P-LCC-44 package in the microprocessor
mode (PMODE = "1") by bit ADF2:ICEC, see "ADF2-Register", page 214.
The following table gives an overview of the control mechanisms of this function in
different settings. The terms "Idle" and "active" of the IOM®-2 interface in Table 7 are
defined as follows:
Idle means that no FSC and DCL clocks are output. Clocks may be applied to pins FSC
and DCL. However, they are ignored by the IEC-Q. Data on pin DIN is ignored. Internally,
the DIN signal will be clamped to ’1’. Pin DOUT is ’floating’, which is the same behavior
as described in "DOUT Driver Modes", page 53.
Semiconductor Group
54
Data Sheet 01.99
INFINEON [ Infineon ]
