PEB 2091
PEF 2091
Electrical Characteristics
8.7.6
Master Clock
8.7.6.1 LT Modes
In LT modes (except COT-512/1536 mode) all timing signals are derived from a system
clock via an external phase locked loop. The clock specifications for these modes are
described below.
For the LT modes COT-512 and COT-1536 the requirements as specified in section “NT
Modes” on page 283 (NT modes) apply.
IEC-Q
Frame Adapt
DCL
R
IOM
FSC
FSC*
%
%
IOM R -Frame
IOM R -Frame
XIN
Clock
Generation
15.36 - MHz Master Clock
System Clock
ITD04262
Figure 119 Clock Requirements in LT Modes
Note 82: FSC*Fictitious FSC indicates ideal FSC-clock (existing master clock divided
by 1920 without delay).
FSCReal FSC (contains phase shift resulting from propagation delays in
divider).
Master Clock
– Nominal Frequency15.36 MHz
– Jitter (peak-to-peak) see Figure 121, page 282
– Max. phase deviation between FSC and fictitious FSC*± 18 µs
– Duty ratio see Figure 120, page 282
Semiconductor Group
281
Data Sheet 01.99
INFINEON [ Infineon ]
