PEB 2091
PEF 2091
Register Description
B2
B2-channel Interrupt
1=
0=
Indicates an interrupt every time B2-channel bytes arrive
Occurs after RB2I and RB2U have been read
Monitor Data Transmit Interrupt
MDA
1=
0=
Indicates an interrupt after the MOSR:MDA or the MOSR:MAB bits
have been activated
Indicates the inactive interrupt status
5.2.2
MASK-Register
Write
Address 0
H
The Interrupt Mask Register (MASK) can selectively mask each interrupt source in the
ISTA register by setting to "1" the corresponding bit.
Reset value: FFH
7
6
5
4
3
2
1
0
D
CICI
CICU
SF
MDR
B1
B2
MDA
D
D-channel mask
1=
Prevents an interrupt ISTA:D to influence the INT pin
0=
Disables the function described above
CICI
CICU
SF
CICI-channel mask IOM®-2
1=
0=
Prevents an interrupt ISTA:CICI to influence the INT pin
Disables the function described above
CICU-channel mask U
1=
0=
Prevents an interrupt ISTA:CICU to influence the INT pin
Disables the function described above
Superframe marker mask
1=
0=
Prevents an interrupt ISTA:SF to influence the INT pin
Disables the function described above
Semiconductor Group
211
Data Sheet 01.99
INFINEON [ Infineon ]
